The Powder Toy

Single chamber FRAM by LBPHacker

LBPHacker
LBPHacker
49 / 2
14th Oct 2016
8th Jul 2018
2048 cell single chamber FRAM. In this demo random values are written to random addresses. Scales pretty well as the more important addressing mechanisms are designed to use constant space rather than logarithmic. *** Added link to the R216K2A.
60hz conv electronic fram electronics subframe filt

Comments

  • Schmolendevice
    Schmolendevice     15th Oct 2016
    @Apparently the Atanasoff-Berry computer literally ran at 60hz while the Zuse relay computers ran at the hz range.
  • Schmolendevice
    Schmolendevice     15th Oct 2016
    @The8BitPotato In terms of architecture and operations per *clock*, maybe, but given that the 6502 runs at around 1 MHz and older computers ran at the kHz range, definitely not in real time.
  • megagate75
    megagate75     15th Oct 2016
    @Schmolendevice True, True
  • The8BitPotato
    The8BitPotato     15th Oct 2016
    Do you think that these subframe computers could be as powerful as early computers (like KIM-1 and such)?
  • LBPHacker
    LBPHacker     15th Oct 2016
    Well, this one has been happening for a long time. It's just that subframe tech introduces so many new possibilities that even today there are still things left uncovered. The stars of this demo are PSTN and FRME. I wasn't the first to use them though, oh no. Schmolendevice and others had been using them way before I even realised that PSTN can be driven with solid sparks.
  • JavelinMaxx
    JavelinMaxx     15th Oct 2016
    omg this is a great step of mankind. recently many innovations are occuring, looks like another revolution in TPT.
  • LBPHacker
    LBPHacker     15th Oct 2016
    *sigh* nope
  • ItsMyStupidNick123
    ItsMyStupidNick123     15th Oct 2016
    LBP means little big planet i have all game of this series (lbp1,lbp2,lbp3)
  • ChaozAirflow
    ChaozAirflow     15th Oct 2016
    Nice !
  • Schmolendevice
    Schmolendevice     15th Oct 2016
    Also, it would be quite hilarious if we never come up with anything better than PSTN based single chamber FRAMs and the expected lag overhead is precisely what makes main/secondary memory access "slower" and makes "dual/shared chamber" CPU caches useful. Every access of the "hard drive" involves a "tedious" pushing of thousands of pixels while cache/RAM solely uses DRAY.