ALU Logic gate help

  • The-Con
    28th Apr 2011 Member 0 Permalink
    Hi
    I have made an ALU logic gate from a circuit diagram and have been having trouble. I have gone through it and I have even made circuit simulations on other programs to confirm that what i did in TPT was wrong. It seems that when I put in inputs to f0 and f1, i get an output in the correct and incorrect area. (at the top there is an OR gate with 4 inputs, and it is the third input that shouldn't be... inputting.)



    If anyone has any comments or advice, please comment.

    edit:This should be in help, but I accidentally put it in creations, sorry.
  • jalfor
    28th Apr 2011 Member 0 Permalink
    I'll have a look, just give me a minute.

    I can't see the problem, when I put in F1 and F2 it gets stopped at the xor gate
  • The-Con
    28th Apr 2011 Member 0 Permalink
    That wasn't the error. here I outline the error:


    I tried moderating the input with aray, but that didn't work.
    I don't think there is meant to be an output.

    (please don't vote, as it does not work.)
  • jalfor
    28th Apr 2011 Member 0 Permalink
    is this it?



    if not, could you give me a truth table
  • dnerd
    28th Apr 2011 Member 0 Permalink
    Oh! you not gates are made backwards, try this:

    P=PSCN
    M=metl
    Pt=PTCT
    B=BTRY
    I=insl
    X=nothing

    MMM
    IIIIIIIM
    BPXPtXP

    the metl is the input.
  • The-Con
    28th Apr 2011 Member 0 Permalink
    @dnerd
    The not gates function as they should, the main problem I have is that they don't seem to respond fast enough.

    @jalfor
    having a constant f2(i referred to it as F0) alters the outputs of other inputs.

    It seems to alter most outputs that involve F0
  • stevenliao98
    28th Apr 2011 Member 0 Permalink
    @The-Con (View Post)
    Just amazing.
  • The-Con
    28th Apr 2011 Member 0 Permalink
    @stevenliao98 (View Post)
    It doesn't really work though. :(
  • jalfor
    28th Apr 2011 Member 0 Permalink
    What I meant with the truth table is. like an xor gate would be

    A is input one, B is input two and O is output

    A=1 B=1 O=0

    A=0 B=1 O=1

    A=1 B=0 O=1

    A=0 B=0 O=0